CIS-4020, Homework #8: Memory Management

Due: Thursday, October 27, 2016

This homework covers memory management and virtual memory. Refer to class notes, including the handout on the 80386 paging mechanism, chapters 12, 15 and 16 in the text, and also the Intel technical documentation (on the class web site on the "kernel development resources" page).

The Alpha processor (a 64 bit machine) uses three level paging with 8 KiB pages. Page table are stored in a single page and page table entries are 64 bits. Only part of the 64 bit addresses generated by software are actually translated to physical addresses. The other bits are ignored. Given this information, how many bits of the address are actually significant? How large is the address space? Repeat this question for 16 KiB pages.
Most modern operating systems do not allow programs to modify themselves in memory while they are running. In general self-modifying programs could just rewrite their own machine code as they execute. How do operating systems prevent this from occuring and what advantage is obtained by implementing such a restriction?
Consider a system with three page frames and a virtual address space of eight pages. Let the page reference string be 3, 1, 4, 2, 3, 3, 6, 7, 1, 3, 2, 3, 2, 5, 2, 0, 5, 7, 0, 1. Show which pages are in memory after each reference for the Optimal, LRU, FIFO, and clock page replacement algorithms. How many page faults does each method produce in this example?
Read about the PAE feature of the IA-32 architecture. In the Intel 64 and IA-32 Architectures Software Developer's Manual, see Volume 3, Chapter 4, Section 4.4, and especially the diagram in section 4.4.2. Answer the following questions.
- Which processor in the IA-32 family first introduced the feature?
- What is the maximum amount of physical memory supported?
- What is the maximum amount of virtual memory accessible to a single process?
- How have the page tables been modified?